PSD834F3A-20JIT データシートの表示（PDF） - STMicroelectronics

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PSD834F3A-20JIT

Flash in-system programmable (ISP) peripherals for 8-bit MCUs, 5 V

STMicroelectronics 

PSD8XXFX

I/O ports

Port D pins can be configured in PSDsoft Express as input pins for other dedicated

functions:

● Address Strobe (ALE/AS, PD0)

● CLKIN (PD1) as input to the macrocells flip-flops and APD counter

● PSD Chip Select input (CSI, PD2). Driving this signal high disables the Flash memory,

SRAM and CSIOP.

Figure 29. Port D structure

DATA OUT

REG.

DQ

WR

ECS[ 2:0]

READ MUX

P

D

B

DATA OUT

OUTPUT

MUX

DATA IN

OUTPUT

SELECT

PORT D PIN

DIR REG.

DQ

WR

ENABLE PRODUCT

TERM (.OE)

CPLD - INPUT

AI02889

16.23

External Chip Select

The CPLD also provides three External Chip Select (ECS0-ECS2) outputs on port D pins

that can be used to select external devices. Each External Chip Select (ECS0-ECS2)

consists of one product term that can be configured active high or low. The output enable of

the pin is controlled by either the output enable product term or the Direction register (see

Figure 30).

Doc ID 7833 Rev 7

77/128

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