CS5460A-BS データシートの表示（PDF） - Cirrus Logic

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CS5460A-BS

Single Phase, Bi-directional Power/Energy IC

Cirrus Logic 

RS

DL0

DL1

EOD

SI[1:0]

Res

EWA

Gi

PC[6:0]

CS5460A

Start a chip reset cycle when set 1. The reset cycle lasts for less than 10 XIN cycles. The bit is

automatically returned to 0 by the reset cycle.

When EOD = 1, EDIR becomes a user defined pin. DL0 sets the value of the EDIR pin.

Default = '0'

When EOD = 1, EOUT becomes a user defined pin. DL1 sets the value of the EOUT pin.

Default = '0'

Allows the EOUT and EDIR pins to be controlled by the DL0 and DL1 bits. EOUT and EDIR can

also be accessed using the Status Register.

0 = Normal operation of the EOUT and EDIR pins. (default)

1 = DL0 and DL1 bits control the EOUT and EDIR pins.

Soft interrupt configuration. Select the desired pin behavior for indication of an interrupt.

00 = active low level (default)

01 = active high level

10 = falling edge (INT is normally high)

11 = rising edge (INT is normally low)

Reserved. These bits must be set to zero.

Allows the output pins of EOUT and EDIR of multiple chips to be connected in a wire-AND, us-

ing an external pull-up device.

0 = normal outputs (default)

1 = only the pull-down device of the EOUT and EDIR pins are active

Sets the gain of the current PGA

0 = gain is 10 (default)

1 = gain is 50

Phase compensation. A 2’s complement number used to set the delay in the voltage channel.

When MCLK = 4.096 MHz and K = 1, the phase adjustment range is about -2.8 to +2.8 degrees

and each step is about 0.04 degrees (this assumes that the power line frequency is 60 Hz). If

(MCLK / K) is not 4.096 MHz, the values for the range and step size should be scaled by the

factor 4.096 MHz / (MCLK / K).

Default setting is 0000000 = 0.0215 degrees phase delay (when MCLK = 4.096 MHz).

DS487F4

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