CS42L50 データシートの表示（PDF） - Cirrus Logic
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CS42L50 Datasheet PDF : 48 Pages
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CS42L50
LRCK
SCLK
SDATA 1 0
Left Channel
Right Channel
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 clocks
Right Justified, 18-Bit Data. Data Valid on Rising Edge of
SCLK. SCLK Must Have at Least 36 Cycles per LRCK
Period.
Figure 28. Right Justified, 18-bit data
LRCK
SCLK
SDATA 1 0
Left Channel
Right Channel
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 clocks
Right Justified, 20-Bit Data. Data Valid on Rising Edge of
SCLK. SCLK Must Have at Least 40 Cycles per LRCK
Period.
Figure 29. Right Justified, 20-bit data
LRCK
SCLK
SDATA
Left Channel
Right Channel
MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB
I2S, up to 24-Bit Data. Data Valid on Rising Edge of
SCLK
Figure 30. I2S, up to 24-bit data
42
DS544PP1
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