STM32F030C8P6TR(2013) データシートの表示（PDF） - STMicroelectronics

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STM32F030C8P6TR
(Rev.:2013)

Value-line ARM®-based 32-bit MCU with up to 256-KB Flash, timers, ADC, communication interfaces, 2.4-3.6 V operation

STMicroelectronics 

Electrical characteristics

STM32F030x4 STM32F030x6 STM32F030x8

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is

executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with

IEC 61967-2 standard which specifies the test board and the pin loading.

Table 40. EMI characteristics

Symbol Parameter

Conditions

Monitored

frequency band

Max vs. [fHSE/fHCLK]

8/48 MHz

Unit

SEMI

Peak level

VDD 3.6 V, TA 25 °C,

LQFP64 package

compliant with IEC

61967-2

0.1 to 30 MHz

30 to 130 MHz

130 MHz to 1GHz

SAE EMI Level

-3

28

dBµV

23

4

-

6.3.12

Electrical sensitivity characteristics

Based on three different tests (ESD, LU) using specific measurement methods, the device is

stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are

applied to the pins of each sample according to each pin combination. The sample size

depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test

conforms to the JESD22-A114/C101 standard.

Table 41. ESD absolute maximum ratings

Symbol

Ratings

Conditions

Class

Maximum

value(1)

Unit

VESD(HBM)

Electrostatic discharge

(human body model)

voltage

VESD(CDM)

Electrostatic discharge

(charge device model)

voltage

TA +25 °C, conforming

to JESD22-A114

2

TA +25 °C, conforming

to JESD22-C101

II

2000

V

500

1. Data based on characterization results, not tested in production.

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up

performance:

 A supply overvoltage is applied to each power supply pin

 A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD 78A IC latch-up standard.

Table 42. Electrical sensitivities

Symbol

Parameter

Conditions

LU Static latch-up class TA +105 °C conforming to JESD78A

Class

II level A

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DocID024849 Rev 1

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