ST7FMC2N6B6(2004) データシートの表示（PDF） - STMicroelectronics

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ST7FMC2N6B6
(Rev.:2004)

8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, BRUSHLESS MOTOR CONTROL, FIVE TIMERS, SPI, LINSCI™

STMicroelectronics 

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

POLARITY REGISTER (MPOL)

Read/Write (some bits write-once)

Reset Value: 0011 1111 (3Fh)

7

6

5

4

3

2

1

0

ZVD REO OP5 OP4 OP3 OP2 OP1 OP0

Bit 7 = ZVD: Z vs D edge polarity.

0: Zero-crossing and End of Demagnetisation

have opposite edges

1: Zero-crossing and End of Demagnetisation

have same edge

Bit 6 = REO: Read on High or Low channel bit

0: Read the BEMF signal on High channels

1: Read on Low channels

Note: This bit always has to be configured whatev-

er the sampling method.

Bits 5:0 = OP[5:0]*: Output channel polarity.

These bits are used together with the OO[5:0] bits

in the MPHST register to control the output chan-

nels.

0: Output channel is Active Low

1: Output channel is Active High.

* Write-once bits; once write-accessed these bits

cannot be re-written unless the processor is reset

(See “Caution: Access to write-once bits” on

page 216.).

Table 76. Output Channel State Control

OP[5:0] bit

0

0

1

1

OO[5:0] bit

0

1

0

1

MCO[5:0] pin

1 (Off)

0 (PWM possible)

0 (Off)

1 (PWM possible)

Warning: OP[5:0] bits in the MPOL register must

be configured as required by the application be-

fore enabling the MCO[5:0] outputs with the MOE

bit in the MCRA register.

218/294

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