ST7FMC2N6B6(2004) データシートの表示（PDF） - STMicroelectronics

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ST7FMC2N6B6
(Rev.:2004)

8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, BRUSHLESS MOTOR CONTROL, FIVE TIMERS, SPI, LINSCI™

STMicroelectronics 

ST7MC1/ST7MC2

LINSCI SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont’d)

9.5.6 Low Power Modes

9.5.7 Interrupts

Mode

WAIT

HALT

Description

No effect on SCI.

SCI interrupts cause the device to exit

from Wait mode.

SCI registers are frozen.

In Halt mode, the SCI stops transmit-

ting/receiving until Halt mode is exit-

ed.

Interrupt Event

Transmit Data Register

Empty

Transmission Com-

plete

Received Data Ready

to be Read

Overrun Error or LIN

Synch Error Detected

Idle Line Detected

Parity Error

LIN Header Detection

Event

Flag

Enable

Control

Bit

TDRE TIE

TC TCIE

RDRF

OR/

LHE

IDLE

PE

LHDF

RIE

ILIE

PIE

LHIE

Exit

from

Wait

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Exit

from

Halt

No

No

No

No

No

No

No

The SCI interrupt events are connected to the

same interrupt vector (see Interrupts chapter).

These events generate an interrupt if the corre-

sponding Enable Control Bit is set and the inter-

rupt mask in the CC register is reset (RIM instruc-

tion).

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