CS8405A-CS(2002) データシートの表示（PDF） - Cirrus Logic

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CS8405A-CS
(Rev.:2002)

96 kHz Digital Audio Interface Transmitter

Cirrus Logic 

11. PIN DESCRIPTION - HARDWARE MODE

CS8405A

COPY/C

VL2+

VD+

VL3+

VL+

VL4+

EMPH

SFMT0

SFMT1

DGND6

DGND3

DGND

RST

APMS

TCBLD

ILRCK

ISCLK

SDIN

TCBL

1 COPY Channel Status Bit/C Bit (Input) - In hardware mode A (CEN = 0), the COPY/C and ORIG pins

determine the state of the Copyright, Pro, and L Channel Status bits in the outgoing AES3 data stream,

see Table 2. In hardware mode B, the COPY/C pin becomes the direct C bit input data pin.

2 Positive Digital Power (Input) - Typically +5 V. VD+ must be +5 V, the other VL+ pins may be operated

6 at (CEN = 0)+3.3 V

20

23

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3 Pre-Emphasis Indicator (Input) - In hardware mode A (CEN = 0), the EMPH pin low sets the 3 empha-

sis channel status bits to indicate 50/15 µs pre-emphasis of the transmitted audio data. If EMPH is high,

then the three EMPH channel status bits are set to 000, indicating no pre-emphasis.

4 Serial Audio Data Format Select (Input) - select the serial audio input port format. See Table 3.

5

7 Digital Ground (Input) - Ground for the digital section.

8

22

9 Reset (Input) - When RST is low, the CS8405A enters a low power mode and all internal states are

reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks are

stable in frequency and phase. This is particularly true in hardware mode with multiple CS8405A

devices, where synchronization between devices is important.

10 Serial Audio Data Port Master/Slave Select (Input) - APMS should be connected to VL+ to set serial

audio input port as a master or connected to DGND to set the port as a slave.

11 Transmit Channel Status Block Direction (Input) - Connect TCBLD to VL+ to set TCBL as an output.

Connect TCBLD to DGND to set TCBL as an input.

12 Serial Audio Input Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDIN

pin.

13 Serial Audio Bit Clock (Input/Output) - Serial bit clock for audio data on the SDIN pin.

14 Serial Audio Data Port (Input) - Audio data serial input pin.

15 Transmit Channel Status Block Start (Input/Output) - When operated as output, TCBL is high during

the first sub-frame of a transmitted channel status block, and low at all other times. When operated as

input, driving TCBL high for at least three OMCK clocks will cause the next transmitted sub-frame to be

the start of a channel status block.

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DS469PP4

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