M25P32-VMN6TPB データシートの表示（PDF） - Numonyx -> Micron

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M25P32-VMN6TPB

32-Mbit, low voltage, serial Flash memory with 75 MHz SPI bus interface

Numonyx -> Micron 

M25P32

Instructions

6.4.4

SRWD bit

The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write

Protect (W/VPP) signal. The Status Register Write Disable (SRWD) bit and Write Protect

(W/VPP) signal allow the device to be put in the Hardware Protected mode (when the Status

Register Write Disable (SRWD) bit is set to 1, and Write Protect (W/VPP) is driven Low). In

this mode, the non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become

read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for

execution.

Figure 11. Read Status Register (RDSR) instruction sequence and data-out

sequence

S

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

C

Instruction

D

Status Register Out

Status Register Out

High Impedance

Q

76543210765432107

MSB

MSB

AI02031E

25/54

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