ST92F124JDV2TC データシートの表示（PDF） - STMicroelectronics

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ST92F124JDV2TC

8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM, E³ ™ (EMULATED EEPROM), CAN 2.0B AND J1850 BLPD

STMicroelectronics 

ST92F124/F150/F250 - I/O PORTS

INPUT/OUTPUT BIT CONFIGURATION (Cont’d)

Figure 81. Basic Structure of an I/O Port Pin

I/O PIN

PUSH-PULL

TRISTATE

OPEN DRAIN

WEAK PULL-UP

FROM

PERIPHERAL

OUTPUT

OUTPUT SLAVE LATCH

ALTERNATE

FUNCTION

INPUT

OUTPUT

BIDIRECTIONAL

OUTPUT

OUTPUT MASTER LATCH

TTL / CMOS

(or Schmitt Trigger)

TO PERIPHERAL

INPUTS AND

INTERRUPTS

INPUT

BIDIRECTIONAL

ALTERNATE

FUNCTION

INPUT LATCH

Figure 82. Input Configuration

I/O PIN

INTERNAL DATA BUS

Figure 83. Output Configuration

I/O PIN

TRISTATE

OUTPUT SLAVE LATCH

TTL / CMOS

(or Schmitt Trigger)

TO PERIPHERAL

INPUTS AND

INTERRUPTS

OPEN DRAIN

PUSH-PULL

OUTPUT SLAVE LATCH

TTL

(or Schmitt Trigger)

TO PERIPHERAL

INPUTS AND

INTERRUPTS

OUTPUT MASTER LATCH

INPUT LATCH

INTERNAL DATA BUS

n

n

OUTPUT MASTER LATCH

INPUT LATCH

INTERNAL DATA BUS

n

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