LFECP3E-5T100I データシートの表示（PDF） - Lattice Semiconductor
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LFECP3E-5T100I Datasheet PDF : 163 Pages
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Lattice Semiconductor
Figure 2-29. Output Register Block
Architecture
LatticeECP/EC Family Data Sheet
ONEG0
From
Routing
OPOS0
CLK1
DQ
D-Type
/LATCH
DQ
Latch
LE*
OUTDDN
0
DO
0
1
1
To sysIO
Buffer
*Latch is transparent when input is low.
Figure 2-30. ODDRXB Primitive
Programmed
Control
DA
DB
CLK
LSR
ODDRXB
Q
Tristate Register Block
The tristate register block provides the ability to register tri-state control signals from the core of the device before
they are passed to the sysI/O buffers. The block contains a register for SDR operation and an additional latch for
DDR operation. Figure 2-31 shows the diagram of the Tristate Register Block.
In SDR mode, ONEG1 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured a D-
type or latch. In DDR mode, ONEG1 is fed into one register on the positive edge of the clock and OPOS1 is
latched. A multiplexer running off the same clock selects the correct register for feeding to the output (D0).
2-25
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