ISPLSI1032-90LJ データシートの表示（PDF） - Lattice Semiconductor

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ISPLSI1032-90LJ

High-Density Programmable Logic

Lattice Semiconductor 

Specifications ispLSI and pLSI 1032

ispLSI 1032 Shift Register Layout

D

A

T

A

Data In

(SDI)

159...

319...

High Order Shift Register

Low Order Shift Register

D

A

T

A

...0

...160

SDO

SDI

10... 7

E2CMOS Cell Array

...

0

SDO

Note: A logic "1" in the Address Shift Register bit position enables the row for programming or verification.

A logic "0" disables it.

11

1996 ISP Encyclopedia

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