dsPIC30F3014/4013
FIGURE 20-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
OST TIME-OUT
PWRT TIME-OUT
TOST
TPWRT
INTERNAL Reset
FIGURE 20-4:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
OST TIME-OUT
PWRT TIME-OUT
TOST
TPWRT
INTERNAL Reset
FIGURE 20-5:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
OST TIME-OUT
PWRT TIME-OUT
INTERNAL Reset
TOST
TPWRT
DS70138E-page 146
© 2007 Microchip Technology Inc.