CS8420-CSR データシートの表示（PDF） - Cirrus Logic

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CS8420-CSR

Digital Audio Sample Rate Converter

Cirrus Logic 

CS8420

10.19 Sample Rate Ratio (1Eh) (Read Only)

7

SRR7

6

SRR6

5

SRR5

4

SRR4

3

SRR3

2

SRR2

1

SRR1

0

SRR0

The Sample Rate Ratio is Fso divided by Fsi. This value is represented as an integer and a

fractional part. The value is meaningful only after the both the PLL and SRC have reached lock,

and the SRC output is being used

SRR[7:6

The integer part of the sample rate ratio

SRR[5:0]

The fractional part of the sample rate ratio

10.20 C-Bit or U-Bit Data Buffer (20h - 37h)

Either channel status data buffer E or user data buffer E (provided UBM bits are set to block mode) is ac-

cessible via these register addresses.

10.21 CS8420 I.D. and Version Register (7Fh) (Read Only)

7

ID3

ID[3:0]

6

5

4

3

ID2

ID1

ID0

VER3

ID code for the CS8420. Permanently set to 0001

2

VER2

VER[3:0]

CS8420 Revision Level:

Revision B is coded as 0001

Revision C is coded as 0011

Revision D is coded as 0100

1

VER1

ID3

VER0

DS245F4

47

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