CS8420-CSZ データシートの表示（PDF） - Cirrus Logic

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CS8420-CSZ

Digital Audio Sample Rate Converter

Cirrus Logic 

CS8420

10.7 Serial Audio Output Port Data Format (06h)

7

SOMS

SOMS

6

SOSF

5

SORES1

4

SORES0

3

SOJUST

2

SODEL

Master/Slave Mode Selector

0 - Serial audio output port is in Slave mode (default)

1 - Serial audio output port is in Master mode

1

SOSPOL

0

SOLRPOL

SOSF

OSCLK frequency (for Master mode)

0 - 64*Fso (default)

1 - 128*Fso

SORES[1:0]

Resolution of the output data on SDOUT and AES3 output when the sample rate converter is

set as the source

00 - 24 bit resolution (default)

01 - 20 bit resolution

10 - 16 bit resolution

11 - Direct copy of the received NRZ data from the AES3 receiver (including C, U, and

V bits, the time slot normally occupied by the P bit is used to indicate the location

of the block start, SDOUT pin only, serial audio output port clock must be derived

from the AES3 receiver recovered clock)

SOJUST

Justification of SDOUT data relative to OLRCK

0 - Left-Justified (default)

1 - Right-Justified (Master mode only)

SODEL

Delay of SDOUT data relative to OLRCK, for left-justified data formats

0 - MSB of SDOUT data occurs in the first OSCLK period after the OLRCK edge

(default)

1 - MSB of SDOUT data occurs in the second OSCLK period after the OLRCK edge

SOSPOL

OSCLK clock polarity

0 - SDOUT transitions occur on falling edges of OSCLK (default)

1 - SDOUT transitions occur on rising edges of OSCLK

SOLRPOL

OLRCK clock polarity

0 - SDOUT data is for the left channel when OLRCK is high (default)

1 - SDOUT data is for the right channel when OLRCK is high

DS245F4

39

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