CS8415A-CS データシートの表示（PDF） - Cirrus Logic
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CS8415A-CS Datasheet PDF : 46 Pages
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CS8415A
15.3.4 Jitter Attenuation
Shown in Figure 21, Figure 22, Figure 23, and Figure 24 are jitter attenuation plots for the various revi-
sions of the CS8415A when used with the appropriate external PLL component values (as noted in
Table 6). The AES3 and IEC60958-4 specifications do not have allowances for locking to sample rates
less than 32 kHz. These specifications state a maximum of 2 dB jitter gain or peaking.
5
5
0
0
−5
−5
−10
−10
−15
−15
−20
−20
10−1
100
101
102
103
104
105
10−1
100
101
102
103
104
105
Jitter Frequency (Hz)
Jitter Frequency (Hz)
Figure 21. Revision A
Figure 22. Revision A1
5
0
−5
−10
−15
−20
−25
10−1
100
101
102
103
104
Jitter Frequency (Hz)
Figure 23. Revision A2 using A1 Values
5
0
−5
−10
−15
−20
−25
105
10−1
100
101
102
103
104
105
Jitter Frequency (Hz)
Figure 24. Revision A2 using A2* Values
DS470F4
45
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