CS8411-CS データシートの表示（PDF） - Cirrus Logic

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CS8411-CS

Digital Audio Interface Receiver

Cirrus Logic 

CS8411 CS8412

FCK - Frequency Clock, PIN 13.

Frequency Clock input that is enabled by bringing SEL low. FCK is compared to the received

clock frequency with the value displayed on F2 through F0. Nominal input value is 6.144 MHz.

E0, E1, E2 - Error Condition, PINS 4-6.

Encoded error information that is enabled by bringing SEL low. The error codes are prioritized

and latched so that the error code displayed is the highest level of error since the last clearing

of the error pins. Clearing is accomplished by bringing SEL high for more than 8 MCK cycles.

F0, F1, F2 - Frequency Reporting Bits, PINS 2-3, 27.

Encoded sample frequency information that is enabled by bringing SEL low. A proper clock on

FCK must be input for at least two thirds of a channel status block for these pins to be valid.

They are updated three times per block, starting at the block boundary.

ERF - Error Flag, PIN 25.

Signals that an error has occurred while receiving the audio sample currently being read from

the serial port. Three errors cause ERF to go high: a parity or biphase coding violation during

the current sample, or an out of lock PLL receiver.

Receiver Interface

RXP, RXN - Differential Line Receivers, PINS 9, 10.

RS422 compatible line receivers.

Phase Locked Loop

MCK - Master Clock, PIN 19.

Low jitter clock output of 256 times the received sample frequency.

FILT - Filter, PIN 20.

An external 1 kΩ resistor and 0.047 µF capacitor is required from FILT pin to analog ground.

DS61F1

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