CS8412-CS データシートの表示（PDF） - Cirrus Logic

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CS8412-CS

Digital Audio Interface Receiver

Cirrus Logic 

CS8411 CS8412

PIN DESCRIPTIONS: CS8412

CS8412

CHANNEL STATUS OUTPUT

C1

CS d / FREQ REPORT 1

Cd/F1 2

CS c / FREQ REPORT 0

Cc/F0 3

CS b / ERROR CONDITION 2

Cb/E2 4

CS a / ERROR CONDITION 1

Ca/E1 5

CS 0 / ERROR CONDITION 0

C0/E0 6

DIGITAL POWER

VD+ 7

DIGITAL GROUND

DGND 8

RECEIVE POSITIVE

RXP 9

RECEIVE NEGATIVE

RXN 10

FRAME SYNC FSYNC 11

SERIAL DATA CLOCK

SCK 12

CHANNEL SELECT / FCLOCK CS12/FCK 13

USER DATA OUTPUT

U 14

28 VERF

27 Ce/F2

26 SDATA

25 ERF

24 M1

23 M0

22 VA+

21 AGND

20 FILT

19 MCK

18 M2

17 M3

16 SEL

15 CBL

VALIDITY + ERROR FLAG

CS e / FREQ REPORT 2

SERIAL OUTPUT DATA

ERROR FLAG

SERIAL PORT MODE SELECT 1

SERIAL PORT MODE SELECT 2

ANALOG POWER

ANALOG GROUND

FILTER

MASTER CLOCK

SERIAL PORT MODE SELECT 2

SERIAL PORT MODE SELECT 3

FREQ/CS SELECT

CS BLOCK START

Power Supply Connections

VD+ - Positive Digital Power, PIN 7.

Positive supply for the digital section. Nominally +5 volts.

VA+ - Positive Analog Power, PIN 22.

Positive supply for the analog section. Nominally +5 volts.

DGND - Digital Ground, PIN 8.

Ground for the digital section. DGND should be connected to same ground as AGND.

AGND - Analog Ground, PIN 21.

Ground for the analog section. AGND should be connected to same ground as DGND.

Audio Output Interface

SCK - Serial Clock, PIN 12.

Serial clock for SDATA pin which can be configured (via the M0, M1, M2, and M3 pins) as an

input or output, and can sample data on the rising or falling edge. As an output, SCK will

generate 32 clocks for every audio sample. As an input, 32 SCK periods per audio sample must

be provided in all normal modes.

DS61F1

29

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