CS8406-CS データシートの表示（PDF） - Cirrus Logic

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CS8406-CS

192 kHz Digital Audio Interface Transmitter

Cirrus Logic 

CS8406

TCBL

(In/Output)

VLRCK

V/C/U

(Input)

Tth

Tsetup

Thold

VCU[0]

VCU[1]

VCU[2]

VCU[3]

VCU[4]

SDIN

(Input)

TXP(N)

(Output)

Data [4]

Data [5]

Data [6]

Data [7]

Data [8]

Z Data [0]

Y Data [1]

X Data [2]

Y Data [3]

X Data [4]

AES3 Transmitter in Stereo mode

Tsetup ≥ 7.5% AES3 frame time

Thold = 0

Tth > 3 OMCK clocks, if TCBL is Input

TCBL

Tth

(In/Output)

VLRCK

U

(Input)

U[0]

U[2]

SDIN

(Input)

TXP(N)

(Output)

Data [4]

Data [5]

Z

Data [0]*

* Assume MMTLR = 0

Data [6]

Data [7]

Y

Data [2]*

Data [8]

X

Data [4]*

TXP(N)

(Output)

Z

Data [1]*

* Assume MMTLR = 1

Y

Data [3]*

AES3 Transmitter in Mono mode

X

Data [5]*

Tsetup ≥ 15% AES3 frame time

Thold = 0

Tth > 3 OMCK clocks, if TCBL is Input

•VLRCK is a virtual word clock, which may not exist, and is used to illustrate the CUV timing.

•VLRCK duty cycle is 50%.

•In stereo mode, VLRCK frequency = AES3 frame rate. In mono mode, VLRCK frequency = 2xAES3 frame rate.

•If the serial audio input port is on slave mode and TCBL is an output, then VLRCK = ILRCK if SILRPOL = 0

and VLRCK = ILRCK if SILRPOL =1.

•If the serial audio input port is in master mode and TCBL is an input, then VLRCK = ILRCK if SILRPOL = 0

and VLRCK = ILRCK if SILRPOL =1.

Figure 8. AES3 Transmitter Timing for C, U, and V Pin Input Data

18

DS580F1

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