CS61310 データシートの表示（PDF） - Cirrus Logic

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CS61310

T1 Line Interface Unit

Cirrus Logic 

CS61310

2.12 Serial Interface

In the Host Mode, pins 24 through 28 serve as a mi-

crocontroller interface. On-chip registers can be

written to via the SDI pin or read from via the SDO

pin at the clock rate determined by SCLK. Through

these registers, a host controller can be used to con-

trol operational characteristics and monitor device

status. The serial port read/write timing is indepen-

dent of the system transmit and receive timing.

Data transfers are initiated by taking the chip select

input, CS, low (CS must initially be high). Address

and input data bits are clocked in on the rising edge

of SCLK. The clock edge on which output data is

stable and valid is determined by CLKE as shown

in Table 2. Data transfers are terminated by setting

CS high. CS may go high no sooner than 50 ns after

the rising edge of the SCLK cycle corresponding to

the last write bit. For a serial data read, CS may go

high any time to terminate the output and set SDO

to high impedance.

Figure 10 shows the timing relationships for data

transfers when CLKE = 0. When CLKE = 1, data

bit D7 is held until the falling edge of the 16th clock

cycle. When CLKE = 0, data bit D7 is held valid

until the rising edge of the 17th clock cycle. SDO

goes high-impedance after CS goes high or at the

end of the hold period of data bit D7.

SDO goes to a high impedance state when not in

use. SDO and SDI may be tied together in applica-

tions where the host processor has a bi-directional

I/O port.

An address/command byte, shown in Figure 10,

points to addresses 0x10 through 0x15 (address

0x10 shown), and precedes a data byte. The first bit

of the address/command byte determines whether a

read or a write is requested. The next six bits con-

tain the address. The last bit is ignored. Data to the

internal registers is input on the eight clock cycles

immediately following the address/command byte.

7

Control Register 1

(CR1)

Control Register 2

(CR2)

Equalizer Gain

(EQGAIN)

RAM Address

(RAM)

Reserved

Set to “0”

TAOS

AIS

X

MSB

0

6

5

4

3

LLOOP RLOOP LB02

LB01

RAMPLSE

RSVD

set to “0”

LOOPDN

LOOPUP

X

X

EQ4

EQ3

-

-

-

-

0

0

0

0

2

CODER

TAZ

RPWDN

EQ2

-

0

1

NLOOP

TxHIZ

EQ1

-

0

0

ADDR

LOS 0x10 R/W

RSVD

set to “0”

0x11 R/W

EQ0 0x12 R

LSB 0x13 R/W

0

0x14

Table 3. Register Map

CS

SCLK

SDI

SDO

CLKE = 0

12

R/W 0 0 0 0 1 0 0 D0 D1 D2 D3 D4 D5 D6 D7

Address/Command Byte

Data Input/Output

D0 D1 D2 D3 D4 D5 D6 D7

Figure 10. Input/Output Timing (showing address 0x10)

DS440PP2

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