CS5541 データシートの表示（PDF） - Cirrus Logic

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CS5541

Low-Power, Low-Voltage, 24-Bit ∆Σ ADC

Cirrus Logic 

3. PIN DESCRIPTIONS

AIN1+ 1

AIN1- 2

VA- 3

VA+ 4

CS 5

SCLK 6

SDI 7

OSC1 8

16 AIN2+

15 AIN2-

14 VREF+

13 VREF-

12 DGND

11 VD+

10 SDO

9 OSC2

CS5541

Clock Generator

OSC1; OSC2 - Master Clock.

An inverting amplifier inside the chip is connected between these pins and can be used with a

crystal to provide the master clock for the device. Alternatively, an external (CMOS

compatible) clock (powered relative to VD+) can be supplied into the OSC1 pin to provide the

master clock for the device.

Control Pins and Serial Data I/O

CS - Chip Select.

When active low, the port will recognize SCLK. When high the SDO pin will output a high

impedance state. CS should be changed when SCLK = 0.

SDI - Serial Data Input.

SDI is the input pin of the serial input port. Data will be input at a rate determined by SCLK.

SDO - Serial Data Output.

SDO is the serial data output. It will output a high impedance state if CS = 1.

SCLK - Serial Clock Input.

A clock signal on this pin determines the input/output rate of the data for the SDI/SDO pins

respectively. This input is a Schmitt trigger to allow for slow rise time signals. The SCLK pin

will recognize clocks only when CS is low.

DS500PP1

21

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