CS53L21-DNZR データシートの表示（PDF） - Cirrus Logic

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CS53L21-DNZR

Low Power, Stereo Analog to Digital Converter

Cirrus Logic 

CS53L21

Power Down PGA X (PDN_PGAX)

Default: 0

0 - Disable

1 - Enable

Function:

PGA channel x will either enter a power-down or muted state when this bit is enabled. See Power Control

1 (Address 02h) Note 1 above.

This bit is used in conjunction with AINx_MUX bits to determine the analog input path to the ADC. Refer to

“ADCX Input Select Bits (AINX_MUX[1:0])” on page 47 for the required settings.

Power Down ADC X (PDN_ADCX)

Default: 0

0 - Disable

1 - Enable

Function:

ADC channel x will either enter a power-down or muted state when this bit is enabled. See Note 1 on page

40.

Power Down (PDN)

Default: 0

0 - Disable

1 - Enable

Function:

The entire A/D will enter a low-power state when this function is enabled. The contents of the control port

registers are retained in this mode.

6.3 MIC Power Control & Speed Control (Address 03h)

7

AUTO

6

SPEED1

5

SPEED0

4

3-ST_SP

3

2

1

0

PDN_MICB PDN_MICA PDN_MICBIAS MCLKDIV2

Auto-Detect Speed Mode (AUTO)

Default: 1

0 - Disable

1 - Enable

Function:

Enables the auto-detect circuitry for detecting the speed mode of the A/D when operating as a slave. When

AUTO is enabled, the MCLK/LRCK ratio must be implemented according to Table 3 on page 30. The

SPEED[1:0] bits are ignored when this bit is enabled. Speed is determined by the MCLK/LRCK ratio.

DS700PP1

41

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