CS53L21-DNZR データシートの表示（PDF） - Cirrus Logic
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CS53L21-DNZR Datasheet PDF : 66 Pages
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CS53L21
Master Mode (Note 9)
Parameters
Symbol Min
Max Units
Output Sample Rate (LRCK)
All Speed Modes
(Note 10)
Fs
-
M------C-----L---K---
Hz
128
LRCK Duty Cycle
SCLK Frequency
SCLK Duty Cycle
LRCK Edge to SDOUT MSB Output Delay
SDOUT Setup Time Before SCLK Rising Edge
SDOUT Hold Time After SCLK Rising Edge
45
1/tP
-
45
td(MSB)
-
ts(SDO-SK)
20
th(SK-SDO)
30
55
%
64•Fs
Hz
55
%
52
ns
-
ns
-
ns
7. After powering up the CS53L21, RESET should be held low after the power supplies and clocks are
settled.
8. See “Example System Clock Frequencies” on page 57 for typical MCLK frequencies.
9. See“Master” on page 30.
10. “MCLK” refers to the external master clock applied.
LRCK
SCLK
ts(LK-SK)
//
//
tP
//
//
SDOUT
td(MSB)
th(SK-SDO)
//
MSB
//
ts(SDO-SK)
MSB-1
Figure 3. Serial Audio Interface Slave Mode Timing
LRCK
SCLK
//
//
tP
//
//
SDOUT
td(MSB)
th(SK-SDO)
//
MSB
//
ts(SDO-SK)
MSB-1
Figure 4. Serial Audio Interface Master Mode Timing
DS700PP1
15
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