CS5464-IS データシートの表示（PDF） - Cirrus Logic

部品番号

コンポーネント説明

メーカー

CS5464-IS

Three-channel, Single-phase Power/Energy IC

Cirrus Logic 

CS5464

7. SYSTEM CALIBRATION

7.1 Channel Offset and Gain Calibration

The CS5464 provides digital DC offset and gain com-

pensation that can be applied to the instantaneous volt-

age and current measurements, and AC offset

compensation to the voltage and current RMS calcula-

tions.

Since the voltage and current channels have indepen-

dent offset and gain registers, system offset and/or

gain can be performed on either channel without the

calibration results from one channel affecting the oth-

er.

The computational flow of the calibration sequences are

illustrated in Figure 13. The flow applies to both the volt-

age channel and current channel.

7.1.1 Calibration Sequence

The CS5464 must be operating in its active state and

ready to accept valid commands. Refer to 5.15 Com-

mands on page 24. The calibration algorithms are de-

pendent on the value N in the Cycle Count Register (see

Figure 13). Upon completion, the results of the calibra-

tion are available in their corresponding register. The

DRDY bit in the Status Register will be set. If the DRDY

bit is to be output on the INT pin, then DRDY bit in the

Mask Register must be set. The initial values in the AC

gain and offset registers do affect the results of the cal-

ibration results.

7.1.1.1 Duration of Calibration Sequence

The value of the Cycle Count Register (N) determines

the number of conversions performed by the CS5464

during a given calibration sequence. For DC offset and

gain calibrations, the calibration sequence takes at least

N + 30 conversion cycles to complete. For AC offset cal-

ibrations, the sequence takes at least 6N + 30 ADC cy-

cles to complete, (about 6 computation cycles). As N is

increased, the accuracy of calibration results will in-

crease.

7.1.2 Offset Calibration Sequence

For DC and AC offset calibrations, the VIN± (V2IN±)

pins of the voltage and IIN± (I2IN±) pins of the current

channels should be connected to their ground reference

level. (see Figure 14.)

External

Connections

0V +-

AIN+

CM +-

AIN-

+

+

XGAIN

-

-

Figure 14. System Calibration of Offset

The AC offset registers must be set to the default

(0x000000).

7.1.2.1 DC Offset Calibration Sequence

Channel gain should be set to 1.0 when performing DC

offset calibration. Initiate a DC offset calibration. The DC

offset registers are updated with the negative of the av-

erage of the instantaneous samples collected over a

computational cycle. Upon completion of the DC offset

calibration the DC offset is stored in the corresponding

DC offset register. The DC offset value will be added to

In

Modulator

Filter

+

+

+

DC Offset

Idcoff, Vdcoff,

I2dcoff, V2dcoff

X

Gain

Ign, Vgn,

I2gn, V2gn

Instantaneous

V, I, V2, I2

X

ΣN

ΣN

RMS

÷N

√

+

+

+

IRMS, VRMS,

I2RMS, V2RMS

Iacoff, Vacoff,

I2acoff, V2acoff

AC Offset

Inverse

÷N

-1

X

= NAMES OF READABLE/WRITABLE REGISTERS.

0.6

RMS

Figure 13. Calibration Data Flow

-1

X

DS682PP1

39

Share Link: