CS5461-IS データシートの表示（PDF） - Cirrus Logic

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CS5461-IS

Single Phase Bi-Directional Power/Energy IC

Cirrus Logic 

CS5461

Step H3 - Clear the Status Register by writing

back the read value in step H0.

Step H4 - Re-enable interrupts.

Step H5 - Return from interrupt service routine.

This handshaking procedure insures that any

new interrupts activated between steps H0 and

H3 are not lost (cleared) by step H3.

4.9.2 INT Active State

The behavior of the INT pin is controlled by the

IMODE and IINV bits of the Configuration Regis-

ter. The pin can be active low (default), active high,

active on a return to logic 0 (pulse-low), or active

on a return to logic 1 (pulse-high). If the interrupt

output signal format is set for either pulse-high or

pulse-low, the duration of the INT pulse will be at

least one DCLK cycle (DCLK = MCLK / K).

4.10 Voltage Sag-Detect Feature

The CS5461 includes Status Register bit, VSAG;

which indicates a sag in the power line voltage.

In order for sag condition to be identified, the mea-

sured VRMS must remain below a set sag threshold

level for a specified period of time.

To activate this feature, a voltage threshold value

must be specified in the Voltage Sag Level Register

(VSAGLevel); and a time-duration must be specified

in the Voltage Sag Duration Register (VSAGDura-

tion). This Time Duration is specified in terms of

A/D cycles.

If VRMS is measured below the level specified in

the VSAGLevel Register for a duration of time great-

er than or equal to the number of A/D conversions

specified in the VSAGDuration Register, then the

VSAG bit in the Status Register will be asserted.

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DS546F2

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