CS5461-IS データシートの表示（PDF） - Cirrus Logic

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CS5461-IS

Single Phase Bi-Directional Power/Energy IC

Cirrus Logic 

CS5461

The CS5461 can be driven by an external oscillator

ranging from 2.5 to 20 MHz, but the K divider val-

ue must be set such that the internal DCLK will run

somewhere between 2.5 MHz and 5 MHz. The K

divider value is set with the K[3:0] bits in the Con-

figuration Register. As an example, if XIN =

MCLK = 15 MHz, and K is set to 5, then DCLK is

3 MHz, which is a valid value for DCLK.

XOUT

C1

Oscillator

Circuit

XIN

C2

DGND

C1 = C2 = 22 pF

Figure 3. Oscillator Connection

4.4 Calibration

4.4.1 Overview of Calibration Process

The CS5461 offers digital calibration for both

channels; AC/DC offset and AC/DC gain. For both

the voltage channel and the current channel, the AC

offset calibration sequence performs an entirely

different function than the DC offset calibration se-

quence. The AC gain and DC gain calibration se-

quences perform the same function, but accomplish

the function using different techniques.

Since both the voltage and current channels have

separate offset and gain registers associated with

them, system offset or system gain can be per-

formed on either channel without the calibration

results from one channel affecting the other.

4.4.2 Calibration Sequence

1. Before Calibration the CS5461 must be operat-

ing in its active state, and ready to accept valid

commands. The ‘DRDY’ bit in the Status Register

should also be cleared.

2. Apply appropriate calibration signals to the in-

puts of the voltage/current channels (discussed next

in Sections 4.4.3 and 4.4.4.)

3. Send the 8-bit calibration command to the

CS5461 serial interface. Various bits within this

command specify the exact type of calibration.

4. After the CS5461 finishes the desired internal

calibration sequence, the DRDY bit is set in the

Status Register to indicate that the calibration se-

quence is complete. The results of the calibration

are now available in the appropriate gain/offset

registers.

4.4.3 Calibration Signal Input Level

For AC/DC gain calibrations, there is an absolute

limit on the RMS/DC voltage levels that are select-

ed for the gain calibration input signals. The maxi-

mum value that the gain register can attain is 4.

Therefore, for either channel, if the voltage level of

a gain calibration input signal is low enough that it

causes the CS5461 to attempt to set either gain reg-

ister higher than 4, the gain calibration result will

be invalid and all CS5461 results obtained while

running A/D conversions will be invalid.

4.4.4 Calibration Signal Frequency

Optimally, the frequency of the calibration signal is

the same frequency as the fundamental power line

frequency of the metered power system.

4.4.5 Input Configurations for Calibra-

tions

Figure 4 shows the basic setup for gain calibration.

When performing a DC gain calibration a positive

DC voltage level must be applied at the inputs of

the voltage/current channels. This voltage should

DS546F2

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