CS4953XX(2008) データシートの表示（PDF） - Cirrus Logic

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CS4953XX
(Rev.:2008)

32-bit Audio Decoder DSP Family with Dual DSP Engine Technology

Cirrus Logic 

CS4953xx Data Sheet

32-bit Audio Decoder DSP Family

HADDR[3:0]

HDATA[7:0]

HEN

HR/W

t mas

t mrwsu

t mah

LSP

t mdhr

t mdd

t mcdr

t mrpw

t mdis

t mrd

MSP

t mrwhld

t mrdtw

HDS

tmrwirqh

HREQ

Figure 9. Parallel Control Port - Motorola® Mode Read Cycle Timing

Y HADDR[3:0]

R HDATA[7:0]

A HEN

IN HR/W

HDS

PRELIM HREQ

t mas

tmah

LSP

t mdsu

t mcdw

t mrwsu

t mdhw

MSP

t mwpw

t mwd

tmrwirql

t mrwhld

Figure 10. Parallel Control Port - Motorola Mode Write Cycle Timing

t mwtrd

DS705PP3

Copyright 2008 Cirrus Logic

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