CS4525 データシートの表示（PDF） - Cirrus Logic

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CS4525

30 W Digital Audio Amplifier with Integrated ADC

Cirrus Logic 

6.1.4.6 Parametric EQ

The CS4525 implements 5 fully programmable parametric EQ filters.

The filters are implemented in the bi-quad form shown below.

x[n]

b0

Z -1

Z -1

CS4525

y[n]

b1

Z -1

a1

Z -1

b2

a2

Figure 16. Bi-Quad Filter Architecture

This architecture is represented by the equation shown below where y[n] represents the output sample

value and x[n] represents the input sample value.

y[n] = b0x[n] + b1x[n-1] + b2x[n-2] + a1y[n-1] + a2y[n-2]

Equation 1. Bi-Quad Filter Equation

The coefficients are represented in binary form by 24-bit signed values stored in 3.21 two’s complement

format. The 3 MSB’s represent the sign bit and the whole-number portion of the decimal coefficient, and

the 21 LSB’s represent the fractional portion of the decimal coefficient. The coefficient values must be in

the range of -4.00000 decimal (80 00 00 hex) to 3.99996 decimal (7F FF FF hex).

The binary coefficient values are stored in registers 0Ah - 54h. Each 24-bit coefficient is split into 3 bytes,

each of which is mapped to an individually accessible register location. See the “Register Quick Refer-

ence” section beginning on page 66 for the specific register locations for each coefficient.

By default, all b0 coefficients are set to 1 decimal, and all other coefficients are set to 0 decimal. This im-

plements a pass-through function.

The parametric equalizers be independently enabled and disabled for channels A and B with the En-

ChAPEq and EnChBPEq bits located in the EQ Config register.

Referenced Control

Register Location

EnChAPEq .......................... “Enable Channel A Parametric EQ (EnChAPEq)” on page 79

EnChBPEq .......................... “Enable Channel B Parametric EQ (EnChBPEq)” on page 79

DS726PP1

33

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