CL-PS7111-VC-A データシートの表示（PDF） - Cirrus Logic

部品番号

コンポーネント説明

メーカー

CL-PS7111-VC-A

Low-Power System-on-a-Chip

Cirrus Logic 

CL-PS7111

Low-Power System-on-a-Chip

5.10.1 Memory Configuration Register 2 — MEMCFG2

31:24

(Boot ROM, CS7)

23:16

(Local SRAM, CS6)

15:8

NCS5 configuration

7:0

NCS4 configuration

The Memory Configuration Register 2 is a 32-bit read/write register that sets the configuration of the two

expansion and ROM selects NCS4–5. Each select is configured with a 1-byte field, starting with expan-

sion select 4.

Each of the six non-reserved byte fields for chip-select configuration in the Memory Configuration regis-

ters are identical and define the number of wait states, the bus width, enable EXPCLK output during

accesses and enable sequential mode access. This arrangement applies to NCS0–3, and to NCS4–5

when the PCMCIA enable bits in the SYSCON2 register are not set. The state of these bits is ignored for

the Boot ROM and local SRAM fields in the MEMCFG2 register. This byte field is defined as follows:

7

CLKEN

6

SQAEN

5:4

Sequential access wait state

3:2

Random access wait state

1:0

Bus width

NOTE: IF PCMCIA is enabled, the CS4/CS5 settings in this register are ignored.

The memory area decoded by CS6 is reserved for the 2 Kbytes of on-chip SRAM and does not require a

configuration field in MEMCFG2. It is automatically set up for 32 bits and no wait state. For the Boot ROM,

it is automatically set up for 8 bits and no wait state.

Chip selects NCS4 and NCS5 are used to select two CL-PS6700 PCMCIA controller devices. These have

a multiplexed 16-bit wide address/data interface, and the configuration bytes in the MEMCFG2 register

have no meaning when these interfaces are enabled.

Bit Description

7 CLKENB: Expansion clock enable. Setting this bit enables the EXPCLK to be active during accesses to the selected

expansion device. This provides a timing reference for devices that need to extend bus cycles using the EXPRDY input.

Back-to-back (but not necessarily Page mode) accesses result in a continuous clock. This bit only affects EXPCLK

when the PLL is being used, that is, in 18.432-MHz mode. When operating in 13-MHz mode, the EXPCLK pin is an

input, so it cannot be affected by this register bit. To save power internally, EXPCLK should always be set to ‘0’ when

operating in 13-MHz mode.

6 SQAEN: Sequential access enable. Setting this bit enables sequential accesses that are on a quad-word boundary to

take advantage of faster access times from devices that support Page mode. The sequential access is faulted after

four words, (to allow video refresh cycles to occur), even if the access is part of a longer sequential access. In addition,

when this bit is not set, all non-sequential accesses have a single idle cycle inserted between them so that the chip

select is deasserted between each access for easier debug.

54

REGISTER DESCRIPTIONS

September 1997

PRELIMINARY DATA BOOK v2.0

Share Link: