CS5397 データシートの表示（PDF） - Cirrus Logic
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CS5397 Datasheet PDF : 40 Pages
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CS5396 CS5397
REGISTER DESCRIPTION
** “default” ==> bit status after power-up-sequence
Analog control (address 00000001)
7
6
5
4
3
2
1
0
fstart
gndcal
aapd
adpd
1bit
0
0
0
0
0
FSTART (Frame start)Default = ‘0’.
This bit must be set to ‘1’ to synchronize the modulator output and the decimation filter input
and is automatically reset to ‘0’ after a “fstart” pulse is sent to the analog and digital block.
GNDCAL (Ground calibration enable)
Default = ‘0’.
Modulator input is tied to internal “Vcom” when this bit is ‘1’.
AAPD (Analog Section of modulator in power down)
Default = ‘0’.
The analog section of the modulator is in power down mode when aapd = ‘1’.
ADPD (Digital Section of modulator in power down)
Default = ‘0’.
The digital section on the modulator is in power down mode when adpd = ‘1’.
TEST BIT
Default =’0’.
Must remain at 0.
Mode (address 00000010)
7
6
5
4
3
128x/64x
cal
change_sign
_LR/LL
_hpen
0
0
0
0
0
2
s/_m
0
1
DFS
0
0
mute
0
128x/64x
Default = ‘0’.
Oversampling ratio is 128 when this bit is ‘1’ and 64 when this bit is ‘0’.
CAL (System calibration enable)
Default = ‘0’.
Setting this bit to ‘1’ will initiate calibration.
This bit is automatically reset to ‘0’ following calibration.
Change_sign (Change Sign enable)
Default = ‘0’.
A ‘1’ will interchange the analog input paths within each channel resulting in a phase inversion
of the analog signal. This bit applies to both channels.
_LR/LL (Left-Right output disable) Default = ‘0’.
If this bit is ‘0’, SDATA1 will output the Left and Right channel data from the sdata1 source and
SDATA2 will output the Left and Right channel data from the sdata2 source as described else-
where in the data sheet.
If this bit is set to ‘1’, the Left channel data from sdata1 source and sdata2 source (stored in
Audio port register) will be sent out in SDATA1. SDATA2 will output all the Right channel data.
DS229PP2
25
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