CS42L55 データシートの表示（PDF） - Cirrus Logic

部品番号

コンポーネント説明

メーカー

CS42L55

Ultra Low Power, Stereo CODEC w/Class H Headphone Amp

Cirrus Logic 

6.3 Power Control 2 (Address 03h)

7

PDN_HPB1

6

PDN_HPB0

5

PDN_HPA1

4

PDN_HPA0

3

PDN_LINB1

2

PDN_LINB0

CS42L55

1

PDN_LINA1

0

PDN_LINA0

6.3.1

Headphone Power Control

Configures how the HPDETECT pin, 29, controls the power for the headphone amplifier.

PDN_HPx[1:0]

00

01

10

11

Headphone Status

Headphone channel is ON when the HPDETECT pin, 29, is LO.

Headphone channel is OFF when the HPDETECT pin, 29, is HI.

Headphone channel is ON when the HPDETECT pin, 29, is HI.

Headphone channel is OFF when the HPDETECT pin, 29, is LO.

Headphone channel is always ON.

Headphone channel is always OFF.

6.3.2

Line Power Control

Configures how the HPDETECT pin, 29, controls the power for the line amplifier.

PDN_LINx[1:0]

00

01

10

11

Line Status

Line channel is ON when the HPDETECT pin, 29, is LO.

Line channel is OFF when the HPDETECT pin, 29, is HI.

Line channel is ON when the HPDETECT pin, 29, is HI.

Line channel is OFF when the HPDETECT pin, 29, is LO.

Line channel is always ON.

Line channel is always OFF.

6.4 Clocking Control 1 (Address 04h)

7

Reserved

6

Reserved

5

4

M/S

INV_SCLK

6.4.1

Master/Slave Mode

Configures the serial port I/O clocking.

M/S

0

1

Application:

Serial Port Clocks

Slave (Input ONLY)

Master (Output ONLY)

“Serial Port Clocking” on page 34

3

SCK=MCK1

2

SCK=MCK0

1

MCLKDIV2

0

MCLKDIS

6.4.2

SCLK Polarity

Configures the polarity of the SCLK signal.

INV_SCLK

0

1

SCLK Polarity

Not Inverted

Inverted

DS773F1

43

Share Link: