C8051F93X-C8051F92X データシートの表示（PDF） - Silicon Laboratories

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C8051F93X-C8051F92X

Single/Dual Battery, 0.9–3.6 V, 64/32 kB, SmaRTClock, 10-Bit ADC MCU

Silicon Laboratories 

C8051F93x-C8051F92x

SFR Definition 21.13. P1: Port1

Bit

7

6

5

4

3

2

1

0

Name

P1[7:0]

Type

R/W

Reset

1

1

1

1

1

1

1

1

SFR Page = All Pages; SFR Address = 0x90; Bit-Addressable

Bit Name

Description

Write

Read

7:0 P1[7:0] Port 1 Data.

0: Set output latch to logic 0: P1.n Port pin is logic

Sets the Port latch logic

LOW.

LOW.

value or reads the Port pin 1: Set output latch to logic 1: P1.n Port pin is logic

logic state in Port cells con- HIGH.

HIGH.

figured for digital I/O.

Note: Pin P1.7 is only available in 32-pin devices.

SFR Definition 21.14. P1SKIP: Port1 Skip

Bit

7

6

5

4

3

2

1

0

Name

P1SKIP[7:0]

Type

R/W

Reset

0

0

0

0

0

0

0

0

SFR Page = 0x0; SFR Address = 0xD5

Bit Name

Function

7:0 P1SKIP[7:0] Port 1 Crossbar Skip Enable Bits.

These bits select Port 1 pins to be skipped by the Crossbar Decoder. Port pins used

for analog, special functions or GPIO should be skipped by the Crossbar.

0: Corresponding P1.n pin is not skipped by the Crossbar.

1: Corresponding P1.n pin is skipped by the Crossbar.

Note: Pin P1.7 is only available in 32-pin devices.

Rev. 1.3

233

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