C8051F93X-C8051F92X データシートの表示（PDF） - Silicon Laboratories

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C8051F93X-C8051F92X

Single/Dual Battery, 0.9–3.6 V, 64/32 kB, SmaRTClock, 10-Bit ADC MCU

Silicon Laboratories 

C8051F93x-C8051F92x

SFR Definition 21.12. P0DRV: Port0 Drive Strength

Bit

7

6

5

4

3

2

1

0

Name

P0DRV[7:0]

Type

R/W

Reset

0

0

0

0

0

0

0

0

SFR Page = 0xF; SFR Address = 0xA4

Bit Name

Function

7:0 P0DRV[7:0] Drive Strength Configuration Bits for P0.7–P0.0 (respectively).

Configures digital I/O Port cells to high or low output drive strength.

0: Corresponding P0.n Output has low output drive strength.

1: Corresponding P0.n Output has high output drive strength.

232

Rev. 1.3

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