C8051T603-GS(2007) データシートの表示（PDF） - Silicon Laboratories

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C8051T603-GS
(Rev.:2007)

Mixed Signal OTP EPROM MCU Family

Silicon Laboratories 

C8051T600/1/2/3/4/5

SFR Definition 5.8. ADC0GTH: ADC0 Greater-Than High Byte

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset Value

11111111

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0 SFR Address:

0xC4

Bits7–0: ADC0 Greater-Than High Byte.

SFR Definition 5.9. ADC0GTL: ADC0 Greater-Than Low Byte

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset Value

11000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0 SFR Address:

0xC3

Bits7–0: ADC0 Greater-Than Low Byte. In 8-bit compatibility mode, this register should be set to 0x00.

SFR Definition 5.10. ADC0LTH: ADC0 Less-Than High Byte

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0 SFR Address:

0xC6

Bits7–0: ADC0 Less-Than High Byte.

SFR Definition 5.11. ADC0LTL: ADC0 Less-Than Low Byte

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0 SFR Address:

0xC5

Bits7–0: ADC0 Less-Than Low Byte. In 8-bit compatibility mode, this register should be set to 0x00.

Rev. 0.5

43

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