C8051F38C-GMR データシートの表示（PDF） - Silicon Laboratories
部品番号
コンポーネント説明
メーカー
C8051F38C-GMR Datasheet PDF : 321 Pages
| |||
C8051F380/1/2/3/4/5/6/7/C
21.5.2. FIFO Double Buffering
FIFO slots for Endpoints1-3 can be configured for double-buffered mode. In this mode, the maximum
packet size is halved and the FIFO may contain two packets at a time. This mode is available for End-
points1-3. When an endpoint is configured for Split Mode, double buffering may be enabled for the IN End-
point and/or the OUT endpoint. When Split Mode is not enabled, double-buffering may be enabled for the
entire endpoint FIFO. See Table 21.3 for a list of maximum packet sizes for each FIFO configuration.
Table 21.3. FIFO Configurations
Endpoint
Number
0
1
2
3
Split Mode
Enabled?
N/A
N
Y
N
Y
N
Y
Maximum IN Packet Size
Maximum OUT Packet Size
(Double Buffer Disabled /
(Double Buffer Disabled /
Enabled)
Enabled)
64
128 / 64
64 / 32
64 / 32
256 / 128
128 / 64
128 / 64
512 / 256
256 / 128
256 / 128
21.5.1. FIFO Access
Each endpoint FIFO is accessed through a corresponding FIFOn register. A read of an endpoint FIFOn
register unloads one byte from the FIFO; a write of an endpoint FIFOn register loads one byte into the end-
point FIFO. When an endpoint FIFO is configured for Split Mode, a read of the endpoint FIFOn register
unloads one byte from the OUT endpoint FIFO; a write of the endpoint FIFOn register loads one byte into
the IN endpoint FIFO.
USB Register Definition 21.6. FIFOn: USB0 Endpoint FIFO Access
Bit
7
6
5
4
3
2
1
0
Name
FIFODATA[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
USB Register Address = 0x20-0x23
Bit
Name
Function
7:0 FIFODATA[7:0] Endpoint FIFO Access Bits.
USB Addresses 0x20-0x23 provide access to the 4 pairs of endpoint FIFOs:
0x20: Endpoint 0
0x21: Endpoint 1
0x22: Endpoint 2
0x23: Endpoint 3
Writing to the FIFO address loads data into the IN FIFO for the corresponding
endpoint. Reading from the FIFO address unloads data from the OUT FIFO for
the corresponding endpoint.
182
Rev. 1.4
Share Link: 