C8051F302-GS データシートの表示（PDF） - Silicon Laboratories

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C8051F302-GS

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F300/1/2/3/4/5

Figure 4.6. SOIC-14 Package Drawing

Table 4.4. SOIC-14 Package Dimensions

Dimension

Min

Max

Dimension

Min

Max

A

---

1.75

L

0.40

1.27

A1

0.10

0.25

L2

0.25 BSC

b

0.33

0.51

Q

0

8

c

0.17

0.25

aaa

0.10

D

8.65 BSC

bbb

0.20

E

6.00 BSC

ccc

0.10

E1

3.90 BSC

ddd

0.25

e

1.27 BSC

Notes:

1. All dimensions shown are in millimeters (mm).

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to JEDEC outline MS012, variation AB.

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for

Small Body Components.

Rev. 2.9

33

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