STM32L152VB(2013) Ver la hoja de datos (PDF) - STMicroelectronics

Número de pieza

componentes Descripción

fabricante

STM32L152VB
(Rev.:2013)

Ultra-low-power 32-bit MCU ARM®-based Cortex®-M3, 128KB Flash, 16KB SRAM, 4KB EEPROM, LCD, USB, ADC, DAC

STMicroelectronics 

STM32L151x6/8/B, STM32L152x6/8/B

9

Revision history

Revision history

on

Table 70. Document revision history

Date

Revision

Changes

02-Jul-2010

01-Oct-2010

16-Dec-2010

25-Feb-2011

1

Initial release.

Removed 5 V tolerance (FT) from PA3, PB0 and PC3 in Table 9:

STM32L15xxx pin definitions on page 36

Updated Table 15: Embedded reset and power control block

2

characteristics on page 51

Updated Table 16: Embedded internal reference voltage on page 53

Added Table 53: ADC clock frequency on page 90

Updated Table 54: ADC characteristics on page 90

Modified consumptions on page 1 and in Section 3.1: Low power

modes on page 13

3

LED_SEG8 removed on PB6

Updated Section 6: Electrical characteristics on page 47

VFQFPN48 replaced by UFQFPN48

Features: updated value of Low-power sleep.

Section 3.3.2: Power supply supervisor: updated note.

Table 9: STM32L15xxx pin definitions: modified main function (after

reset) and alternate function for OSC_IN and OSC_OUT pins; modified

footnote 5; added footnote to OSC32_IN and OSC32_OUT pins; C1

and D1 removed on PD0 and PD1 pins (TFBGA64 column).

Section 3.11: DAC (digital-to-analog converter): updated bullet list.

Table 11: Voltage characteristics on page 49: updated footnote 3

regarding IINJ(PIN).

Table 12: Current characteristics on page 49: updated footnote 4

regarding positive and negative injection.

Table 15: Embedded reset and power control block characteristics on

page 51: updated typ and max values for TRSTTEMPO (VDD rising, BOR

enabled).

Table 17: Current consumption in Run mode, code with data

4

processing running from Flash on page 54: removed values for HSI

clock source (16 MHz), Range 3.

Table 18: Current consumption in Run mode, code with data

processing running from RAM on page 55: removed values for HSI

clock source (16 MHz), Range 3.

Table 19: Current consumption in Sleep mode on page 56: removed

values for HSI clock source (16 MHz), Range 3 for both RAM and

Flash; changed units.

Table 20: Current consumption in Low power run mode on page 57:

updated parameter and max value of IDD Max (LP Run).

Table : on page 58: updated symbol, parameter, and max value of IDD

Max (LP Sleep).

Table 18: Typical and maximum current consumptions in Stop mode:

updated values for IDD (Stop with RTC) - RTC clocked by LSE external

clock (32.768 kHz), regulator in LP mode, HSI and HSE OFF (no

independent watchdog).

Doc ID 17659 Rev 8

117/121

Share Link: