R5F211A2SP-U0 Ver la hoja de datos (PDF) - Renesas Electronics

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R5F211A2SP-U0

RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER R8C FAMILY / R8C/1x SERIES

Renesas Electronics 

R8C/1A Group, R8C/1B Group

20. Usage Notes

20.2 Notes on Interrupts

20.2.1 Reading Address 00000h

Do not read address 00000h by a program. When a maskable interrupt request is acknowledged, the CPU reads

interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence. At

this time, the acknowledged interrupt IR bit is set to 0.

If address 00000h is read by a program, the IR bit for the interrupt which has the highest priority among the

enabled interrupts is set to 0. This may cause the interrupt to be canceled, or an unexpected interrupt to be

generated.

20.2.2 SP Setting

Set any value in the SP before an interrupt is acknowledged. The SP is set to 0000h after reset. Therefore, if an

interrupt is acknowledged before setting a value in the SP, the program may run out of control.

20.2.3 External Interrupt and Key Input Interrupt

Either “L” level or “H” level of at least 250 ns width is necessary for the signal input to pins INT0 to INT3 and

pins KI0 to KI3, regardless of the CPU clock.

20.2.4 Watchdog Timer Interrupt

Reset the watchdog timer after a watchdog timer interrupt is generated.

Rev.1.30 Dec 08, 2006 Page 297 of 315

REJ09B0252-0130

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