STM32F030C8P6TR(2013) Ver la hoja de datos (PDF) - STMicroelectronics
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fabricante
STM32F030C8P6TR
(Rev.:2013)
(Rev.:2013)
STMicroelectronics
STM32F030C8P6TR Datasheet PDF : 88 Pages
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Electrical characteristics
STM32F030x4 STM32F030x6 STM32F030x8
Table 44. I/O static characteristics (continued)
Symbol Parameter
Conditions
Min
Typ
Max
Unit
TC and TTa I/O
VIH
High level input FT and FTf I/O
voltage
BOOT0
0.445 VDD+0.398(1) -
0.5 VDD+0.2(1)
-
0.2 VDD+0.95(1)
-
-
-
V
-
All I/Os except BOOT0 pin
0.7 VDD
-
-
TC and TTa I/O
-
200(1)
-
Vhys
Schmitt trigger
hysteresis
FT and FTf I/O
BOOT0
-
100(1)
-
mV
-
300(1)
-
Ilkg
Input leakage
current (2)
Weak pull-up
RPU equivalent
resistor (4)
TC, FT and FTf I/O
TTa in digital mode
VSS VIN VDD
TTa in digital mode
VDD VIN VDDA
TTa in analog mode
VSS VIN VDDA
FT and FTf I/O (3)
VDD VIN 5 V
VIN VSS
-
-
0.1
-
-
1
µA
-
-
0.2
-
-
10
25
40
55
k
Weak pull-down
RPD equivalent
resistor (4)
VIN VDD
25
40
55
k
CIO
I/O pin
capacitance
-
5
-
pF
1. Data based on design simulation only. Not tested in production.
2. Leakage could be higher than maximum value, if negative current is injected on adjacent pins. Refer to
Table 43: I/O current injection susceptibility.
3. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled.
4. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS.
This MOS/NMOS contribution to the series resistance is minimum (~10% order).
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 16 for standard I/Os, and in Figure 17 for
5 V tolerant I/Os.
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