CS8416-CS Ver la hoja de datos (PDF) - Cirrus Logic

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CS8416-CS

192 kHz Digital Audio Interface Receiver

Cirrus Logic 

CS8416

RST

9 Reset (Input) - When RST is low, the CS8416 enters a low power mode and all internal states are

reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks

are stable in frequency and phase.

AD0/CS

14 Address Bit 0 (I2C) / Control Port Chip Select (SPI) (Input) - A falling edge on this pin puts the

CS8416 into SPI control port mode. With no falling edge, the CS8416 defaults to I2C mode. In I2C

mode, AD0 is a chip address pin. In SPI mode, CS is used to enable the control port interface on the

CS8416

AD1/CDIN

15 Address Bit 1 (I2C) / Serial Control Data in (SPI) (Input) - In I2C mode, AD1 is a chip address pin. In

SPI mode, CDIN is the input data line for the control port interface

SCL/CCLK 16 Control Port Clock (Input) - Serial control interface clock and is used to clock control data bits into and

out of the CS8416.

SDA/

CDOUT

17 Serial Control Data I/O (I2C) / Data Out (SPI) (Input/Output) - In I2C mode, SDA is the control I/O data

line. SDA is open drain and requires an external pull-up resistor to VL+. In SPI mode, CDOUT is the

output data from the control port interface on the CS8416

AD2/GPO2 18 General Purpose Output 2 (Output) - If using the I2C control port, this pin must be pulled high or low

through a 47 kΩ resistor. See “General Purpose Outputs” on page 22 for GPO functions.

GPO1

19 General Purpose Output 1 (Output) See “General Purpose Outputs” on page 22 for GPO functions.

GPO0

20 General Purpose Output 0 (Output) See “General Purpose Outputs” on page 22 for GPO functions.

SDOUT

26 Serial Audio Output Data (Output) - Audio data serial output pin. This pin must be pulled high to VL+

through a 47 KΩ resistor to place the part in Software Mode.

OLRCK

28 Serial Audio Output Left/Right Clock (Input/Output) - Word rate clock for the audio data on the

SDOUT pin. Frequency will be the output sample rate (Fs)

OSCLK

27 Serial Audio Output Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT pin

OMCK

25 System Clock (Input) - When the OMCK System Clock Mode is enabled using the SWCLK bit in the

Control 1 register, the clock signal input on this pin is output through RMCK. OMCK serves as

reference signal for OMCK/RMCK ratio expressed in register 24

RMCK

24 Input Section Recovered Master Clock (Output) - Input section recovered master clock output when

PLL is used. Frequency defaults to 256x the sample rate (Fs) and may be set to 128x. It may also be

tri-stated by the RXD bit in the Control 4 register (04h).

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DS578PP2

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