CS8403A-CS Ver la hoja de datos (PDF) - Cirrus Logic
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CS8403A-CS Datasheet PDF : 33 Pages
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CS8403A CS8404A
The channel status data cyclic redundancy check
character (C.S. byte 23) is always generated inde-
pendently for channels A and B and is transmitted
at the end of the channel status block.
Data should not be input through the channel status
port, C, during the CRCC byte time frame, since in-
puts on C are logically OR’ed with internally gen-
erated data.
Consumer Mode
Setting PRO high places the CS8404A in consumer
mode which redefines the pins as shown in Figure
20. In consumer mode, channel status bit 0 is trans-
mitted as a zero and channel status bits 2, 3, 8, 9,
15, 24, and 25 are controlled via dedicated pins.
The pins are actually the inverse of the bit so if pin
C2 is tied high, channel status bit 2 will be trans-
mitted as a zero. Also, FC0 and FC1 are encoded
versions of channel status bits 24 and 25, which de-
fine the sample frequency. When FC0 and FC1 are
both high, the part is placed in a CD submode
which activates the CD subcode port. This sub-
mode is described in detail in the next section. Ta-
ble 5 describes the encoding of C24 and C25
through the FC1 and FC0 pins. According to AES/
EBU standards, C2 is copy prohibit/permit, C3
specifies pre-emphasis, C8 and C9 define the cate-
gory code, and C15 identifies the generation status
of the transmitted material (i.e. first generation,
second generation).
FC1 FC0 C24 C25
Comments
0
0
0
0 44.1 kHz
0
1
0
1 48.0 kHz
1
0
1
1 32.0 kHz
1
1
0
0 44.1 kHz, CD Mode
Table 5. Sample Frequency Encoding
SDATA
SCK
FSYNC
8
6
7
M2 M1 M0
23 22 21
Serial
Port
Logic
Audio
Aux
C
U
V
10
11
9
Registers
C Bits
U Bits
Validity
Mux
Biphase
Mark
Encoder
Timing
Line
Driver
20 TXP
17 TXN
16 RST
Preamble
Parity
+5V
2 3 24 4 1 13 14 12
PRO FC0 FC1 C2 C3 C8 C9 C15
15 5
CBL MCK
Figure 20. CS8404A Block Diagram - Consumer Mode
24
DS239PP1
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