CS4207-DNZ Ver la hoja de datos (PDF) - Cirrus Logic
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CS4207-DNZ Datasheet PDF : 148 Pages
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CS4207
7.2 Analog Inputs
The analog inputs of the CS4207 can be configured as single-ended, pseudo-differential, or fully differential
topologies. See Tables 5 and 6 for the register settings required to place the analog inputs into the appro-
priate topology. The ADC1 Gain, ADC2 Gain, ADC1 PGA Mode, and ADC2 PGA Mode bits are located in
the ADC Configuration (CIR = 0002h) register of the Vendor Processing Widget (Node ID = 11h).
Single-Ended
Pseudo-Differential (default)
ADC1 Gain
0
0
ADC1 PGA Mode
1
0
Table 5. Line In 1/Mic In 2 Input Topology Register Settings
Figure
11
12
Single-Ended
Pseudo-Differential (default)
Fully Differential
ADC2 Gain (Note:)
0
0
1
ADC2 PGA Mode
1
0
0
Figure
11
12
13
Table 6. Mic In 1/Line In 2 Input Topology Register Settings
Note: Alternatively, the BTL bit in the Mic In 1/Line In 2 EAPD/BTL Enable control of the Mic In 1/Line In
2 Pin Widget (Node ID = 0Dh) may be set to ‘1’b to put ADC2 in fully differential mode.
Both analog stereo input pairs may be used with single-ended line or microphone inputs. In this configura-
tion the LINEIN_C-, MICIN_L-, and MICIN_R- pins are internally disconnected and should be left floating.
See Figure 11 for the recommended single-ended input filter.
Left Analog Input 1 //
Right Analog Input 1 //
100 k
100 k
**
100
1 µF
100 **
1 µF
Note 1
* 1800 pF
*
1800 pF
CS4207
LINEIN_L+
N/C LINEIN_C- VCOM
LINEIN_R+
+
PGA
-
-
PGA
+
Left Analog Input 2 //
Right Analog Input 2 //
100 k
100 k
**
100
1 µF
* 1800 pF
MICIN_L-
N/C
MICIN_L+
VCOM
100 **
1 µF
*
1800 pF
MICIN_R+
N/C MICIN_R-
VCOM
-
PGA
+
+
PGA
-
* NPO/C0 G dielectric capacitors.
** Low ESR, X7 R/X5R dielectric capacitors.
AGND
Note:
1. These capacitors serve as a charge reservoir for the internal switched capacitor ADC
modulators and should be placed as close as possible to the inputs.
Figure 11. Single-Ended Input Filter
DS880F4
139
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