CS4385(2004) Ver la hoja de datos (PDF) - Cirrus Logic

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CS4385
(Rev.:2004)

114 dB, 192 kHz 8-Channel D/A Converter

Cirrus Logic 

CS4385

5.4.4 INVALID DSD DETECT (INVALID_DSD)

Function:

When set to 1, the DSD processor checks for greater than 24 out of 28 bits of the same value and, if de-

tected, will attenuate the data sent to the DACs. The MUTEC pins go active according to the DAMUTE

register.

When set to 0 (default), this function is disabled.

5.4.5 DSD PHASE MODULATION MODE SELECT (DSD_PM_MODE)

Function:

When set to 0 (default), the 128Fs (BCKA) clock should be input to DSD_SCLK for phase modulation

mode. (See Figure 22 on page 26)

When set to 1, the 64Fs (BCKD) clock should be input to DSD_SCLK for phase modulation mode.

5.4.6 DSD PHASE MODULATION MODE ENABLE (DSD_PM_EN)

Function:

When set to 1, DSD phase modulation input mode is enabled and the DSD_PM_MODE bit should be set

accordingly.

When set to 0 (default), this function is disabled (DSD normal mode).

5.5 Filter Control (address 05h)

7

Reserved

0

6

Reserved

0

5

Reserved

0

4

Reserved

0

3

Reserved

0

2

Reserved

0

1

Reserved

0

0

FILT_SEL

0

5.5.1 INTERPOLATION FILTER SELECT (FILT_SEL)

Function:

When set to 0 (default), the Interpolation Filter has a fast roll off.

When set to 1, the Interpolation Filter has a slow roll off.

The specifications for each filter can be found in the Analog characteristics table, and response plots can

be found in figures 28 to 51 found on the page 26.

DS671A1

41

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