FDC6301N Datasheet - Fairchild Semiconductor

General Description
These dual N-Channel logic level enhancement mode field effect transistors are produced using Fairchild s proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for digital transistors. Since bias resistors are not required, these N-Channel FETs can replace several digital transistors, with a variety of bias resistors.

FEATUREs
■ 25 V, 0.22 A continuous, 0.5 A Peak.
    RDS(ON) = 5 Ω @ VGS= 2.7 V RDS(ON) = 4 Ω @ VGS= 4.5 V.
■ Very low level gate drive requirements allowing direct operation in 3V circuits. VGS(th) < 1.5V.
■ Gate-Source Zener for ESD ruggedness. >6kV Human Body Model.