CS493295 View Datasheet(PDF) - Cirrus Logic
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Description
MFG CO.
CS493295 Datasheet PDF : 90 Pages
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CS49300 Family DSP
6.2.1. Intel Parallel Host
Communication Mode
The Intel parallel host communication mode is
implemented using the pins given in Table 6.
The INTREQ pin is controlled by the application
code when a parallel host communication mode
has been selected. When the code supports
INTREQ notification, the INTREQ pin is asserted
whenever the DSP has an outgoing message for
the host. This same information is reflected by the
HOUTRDY bit of the Host Control Register (A[1:0]
= 01b).
INTREQ is useful for informing the host of
unsolicited messages. An unsolicited message is
defined as a message generated by the DSP
without an associated host read request.
Unsolicited messages can be used to notify the
host of conditions such as a change in the
Mnemonic
Pin Name Pin Number
Chip Select
CS
18
Write Enable
WR
4
Output Enable
RD
5
Register Address Bit 1 A1
6
Register Address Bit 0 A0
7
Interrupt Request
INTREQ 19
DATA7
DATA7
8
DATA6
DATA6
9
DATA5
DATA5
10
DATA4
DATA4
11
DATA3
DATA3
14
DATA2
DATA2
15
DATA1
DATA1
16
DATA0
DATA0
17
Table 6. Intel Mode Communication Signals
The flow diagram shown in Figure 24 illustrates the
sequence of events that define a one-byte write in
Intel mode. The protocol presented in Figure 24
will now be described in detail.
1) The host must first drive the A1 and A0 register
address pins of the CS493XX with the address
of the desired Parallel I/O Register.
Host Message:
A[1:0]==00b.
Host Control:
A[1:0]==01b.
PCMDATA:
A[1:0]==10b.
CMPDATA:
A[1:0]==11b.
2) The host then indicates that the selected
register will be written. The host initiates a write
cycle by driving the CS and WR pins low.
3) The host drives the data byte to the DATA[7:0]
pins of the CS493XX.
4) Once the setup time for the write has been met,
the host ends the write cycle by driving the CS
and WR pins high.
6.2.1.2. Reading a Byte in Intel Mode
Information provided in this section is intended as
a functional description of how to write control
information to the CS493XX. The system designer
must insure that all of the timing constraints of the
Intel Parallel Host Mode Read Cycle are met.
ADDRESS A PARALLEL I/O REGISTER
(A[1:0] SET APPROPRIATELY
CS (LOW)
WR (LOW)
incoming audio data type (e.g. PCM --> AC-3).
6.2.1.1. Writing a Byte in Intel Mode
Information provided in this section is intended as
a functional description of how to write control
information to the CS493XX. The system designer
must insure that all of the timing constraints of the
Intel Parallel Host Mode Write Cycle are met.
WRITE BYTE TO
DATA [7:0]
CS (HIGH)
WR (HIGH)
Figure 24. Intel Mode, One-Byte Write Flow Dia-
46
DS339F7
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