STM32WB55xx STM32WB35xx
Electrical characteristics
Figure 31. SPI timing diagram - slave mode and CPHA = 0
NSS input
MISO
OUTPUT
(SI)
MOSI
INPUT
MSB OUT
MSB IN
(SI)
BIT6 OUT
BIT1 IN
LSB OUT
LSB IN
Figure 32. SPI timing diagram - slave mode and CPHA = 1
NSS input
tSU(NSS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCKH)
tw(SCKL)
MISO
OUTPUT
MOSI
INPUT
ta(SO)
tsu(SI)
tc(SCK)
tv(SO)
MSB OUT
th(SI)
MSB IN
th(SO)
BIT6 OUT
BIT 1 IN
1. Measurement points are set at CMOS levels: 0.3 VDD and 0.7 VDD.
th(NSS)
tr(SCK)
tf(SCK)
tdis(SO)
LSB OUT
LSB IN
ai14135b
DS11929 Rev 10
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