CL7256SRC208-10 View Datasheet(PDF) - Clear Logic
Part Name
Description
MFG CO.
CL7256SRC208-10 Datasheet PDF : 16 Pages
| |||
CL7256E and CL7256S Laser Processed Logic Devices
AC Electrical Specifications cont.
Internal Timing Parameters[4]
Symbol
Parameter
tiN
Input pad and buffer delay
tIO
I/O input pad and buffer delay
tFIN
Fast input delay
tSEXP Shared expander delay
tPEXP Parallel expander delay
tLAD
Logic array delay
tLAC
Logic control array delay
tIOE
Internal output enable delay
tOD1
Output buffer and pad delay
Slow slew rate = off, VCCIO = 5.0 V
tOD2
Output buffer and pad delay
Slow slew rate = off, VCCIO = 3.3 V
Output buffer and pad delay
tOD3 Slow slew rate = on,
VCCIO = 5.0 V or 3.3 V
tZX1
Output buffer enable delay
Slow slew rate = off, VCCIO = 5.0 V
tZX2
Output buffer enable delay
Slow slew rate = off, VCCIO = 3.3 V
Output buffer enable delay
tZX3
Slow slew rate = on,
VCCIO = 5.0 V or 3.3 V
tXZ
Output buffer disable delay
tSU
Register setup time
tH
Register hold time
tFSU Register setup time of fast input
tFH
Register hold time of fast input
tRD
Register delay
tCOMB Combinatorial delay
tIC
Array clock delay
tEN
Register enable time
tGLOB Global control delay
tPRE Register preset time
tCLR Register clear time
tLIA
LIA delay
Conditions
CL = 35 pF
CL = 35 pF
CL = 35 pF
CL = 35 pF
CL = 35 pF
CL = 35 pF
CL = 5 pF[3]
Page 12
Speed: -12P
Min Max
1.0
1.0
1.0
7.0
1.0
7.0
5.0
2.0
1.0
Speed: -12
Min Max
2.0
Unit
ns
2.0
ns
1.0
ns
7.0
ns
1.0
ns
5.0
ns
5.0
ns
2.0
ns
3.0
ns
2.0
4.0
ns
5.0
7.0
ns
6.0
6.0
ns
7.0
7.0
ns
10.0
10.0 ns
6.0
6.0
ns
1.0
4.0
ns
6.0
4.0
ns
4.0
2.0
ns
0.0
2.0
ns
2.0
1.0
ns
2.0
1.0
ns
5.0
5.0
ns
7.0
5.0
ns
2.0
0.0
ns
4.0
3.0
ns
4.0
3.0
ns
1.0
1.0
ns
7K tbl 07E2
Share Link: 