CS8900-CQ View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS8900-CQ

Highly-Integrated ISA Ethernet Controller

Cirrus Logic 

CS8900

In the interrupt service routine, the BufEvent

register (register C), bit RxDMA Frame (bit 7)

indicates that one or more receive frames were

transferred using DMA. The software driver

should maintain a pointer (e.g. PDMA_START)

that will point to the beginning of a new frame.

After the CS8900 is initialized and before any

frame is received, pointer PDMA_START points to

the beginning of the DMA buffer memory area.

The first read of the DMA Frame Count, CDMA,

commits the memory covered by the CDMA

count, and the DMA cannot overwrite this com-

mitted space until the space is freed. The driver

then processes the frames described by the

CDMA count and makes a second read of the

DMA frame count. This second read frees the

buffer memory space described by the CDMA

counter.

DMA Buffer

Base Address

"Holes" due to

double-word

alignment

RxStatus - Frame 1

RxLength - Frame 1

Frame 1

DMA Byte Count

(PacketPage base + 012Ah)

RxStatus - Frame 2

RxLength - Frame 2

Frame 2

RxStatus - Frame 3

RxLength - Frame 3

DMA Start of Frame

register (PacketPage

base + 0126H)

points here.

Frame 3

Figure 5.6. Example of Frames Stored in DMA Buffer

92

DS150PP2

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