CS8900-CQ View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS8900-CQ

Highly-Integrated ISA Ethernet Controller

Cirrus Logic 

CS8900

Table 3.1 presents one possible way of connect-

ing the interrupt request pins to the ISA bus that

utilizes commonly available interrupts and facili-

tates board layout.

DMA Signals

The CS8900 interfaces directly to the host DMA

controller to provide DMA transfers of receive

frames from CS8900 memory to host memory.

The CS8900 has three pairs of DMA pins that

can be connected directly to the three 16-bit

DMA channels of the ISA bus. Only one DMA

channel is used at a time. It is selected during

initialization by writing the number of the de-

sired channel (0, 1 or 2) into PacketPage

Memory base + 0024h. Unused DMA pins are

placed in a high-impedance state. The selected

DMA request pin goes high when the CS8900

has received frames to transfer to the host mem-

ory via DMA. If the DMABurst bit (register 17,

BusCTL, Bit B) is set, the pin goes low after the

DMA operation is complete. If the DMABurst

bit is clear, the pin goes low 32 µs after the start

of a DMA transfer.

CS8900 DMA

Signal (Pin #)

DMARQ0 (Pin 15)

DMACK0 (Pin 16)

DMARQ1 (Pin 13)

DMACK1 (Pin 14)

DMARQ2 (Pin 11)

DMACK2 (Pin 12)

ISA DMA

Signal

DRQ5

DACK5

DRQ6

DACK6

DRQ7

DACK7

PacketPage

base + 0024h

0000h

0001h

0002h

Table 3.2. DMA Assignments

The DMA pin pairs are arranged on the CS8900

to facilitate board layout. Crystal recommends

the configuration in Table 3.2 when connecting

these pins to the ISA bus.

For a description of DMA mode, see Section

5.4.

3.3 Reset and Initialization

3.3.1 Reset

Seven different conditions cause the CS8900 to

reset its internal registers and circuits.

External Reset, or ISA Reset: There is a chip-

wide reset whenever the RESET pin is high for

at least 400 ns. During a chip-wide reset, all cir-

cuitry and registers in the CS8900 are reset.

Power-Up Reset: When power is applied, the

CS8900 maintains reset until the voltage at the

supply pins reaches approximately 2.5 V. The

CS8900 comes out of reset once Vcc is greater

than approximately 2.5 V and the crystal oscilla-

tor has stabilized.

Power-Down Reset: If the supply voltage drops

below approximately 2.5 V, there is a chip-wide

reset. The CS8900 comes out of reset once the

power supply returns to a level greater than ap-

proximately 2.5 V and the crystal oscillator has

stabilized.

EEPROM Reset: There is a chip-wide reset if an

EEPROM checksum error is detected (see Sec-

tion 3.1).

Software Initiated Reset: There is a chip-wide

reset whenever the RESET bit (Register 15,

SelfCTL, Bit 6) is set.

Hardware (HW) Standby or Suspend: The

CS8900 goes though a chip-wide reset whenever

it enters or exits either HW Standby mode or

HW Suspend mode (see Section 3.7 for more in-

formation about HW Standby and Suspend).

Software (SW) Suspend: Whenever the CS8900

enters SW Suspend mode, all registers and cir-

cuits are reset except for the ISA I/O Base

Address register (located at PacketPage base +

0020h) and the SelfCTL register (Register 15).

DS150PP2

15

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