CS8900-CQ View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS8900-CQ

Highly-Integrated ISA Ethernet Controller

Cirrus Logic 

CS8900

15.0 Glossary of Terms

Acronyms

AUI

CRC

CS

CSMA/CD

DA

EEPROM

EOF

FCS

FDX

IA

IPG

ISA

LA

LLC

MAC

MAU

MIB

RX

SA

SFD

SNMP

SOF

SQE

TDR

TX

UTP

Attachment Unit Interface

Cyclic Redundancy Check

Carrier Sense

Carrier Sense Multiple Access with Collision Detection

Destination Address

Electrically Erasable Programmable Read Only Memory

End-of-Frame

Frame Check Sequence

Full Duplex

Individual Address

Inter-Packet Gap

Industry Standard Architecture

ISA Latchable Address Bus (LA17 - LA23)

Logical Link Control

Media Access Control

Medium Attachment Unit

Management Information Base

Receive

Source Address or ISA System Address Bus (SA0 - SA19)

Start-of-Frame Delimiter

Simple Network Management Protocol

Start-of-Frame

Signal Quality Error

Time Domain Reflectometer

Transmit

Unshielded Twisted Pair

Definitions

Cyclic Redundancy Check

The method used to compute the 32-bit frame check sequence (FCS).

Frame Check Sequence

The 32-bit field at the end of a frame that contains the result of the cyclic redundancy check

(CRC).

Frame

An Ethernet string of data bits that includes the Destination Address (DA), Source Address

(SA), optional length field, Logical Link Control data (LLC data), pad bits (if needed) and

Frame Check Sequence (FCS).

126

DS150PP2

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