CS4812 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS4812 Datasheet PDF : 36 Pages
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CS4812
SET CS LOW
WRITE ADDRESS BYTE
WITH R/W BIT = 0
WRITE MAP BYTE
TOGGLE CS
WRITE ADDRESS BYTE
WITH R/W BIT = 1
READ DATA BYTE
N
REQ LOW?
Y
SET CS LOW
WRITE ADDRESS BYTE
WITH R/W BIT = 0
WRITE MAP BYTE FOR
DSP OUTPUT REGISTER
(MAP = 0X27)
TOGGLE CS
WRITE ADDRESS BYTE
WITH R/W BIT = 1
MORE BYTES
Y
TO READ?
N
SET CS HIGH
READ DATA BYTE
FROM DSP OUTPUT REGISTER
Y
REQ STILL LOW?
N
Figure 18. SPI Slave Mode Read Flow Diagram
SET CS HIGH
Figure 19. SPI Slave Mode Read from DSP Core
Flow Diagram using DSP REQ
should be issued by the bus master, thus complet-
ing the transfer.
2. If data is written to the serial control port output
register prior to the rising edge of CCLK for the D2
data bit, REQ will remain asserted. The bus master
should continue to shift out this new byte.
3. If data is placed in the SCP output register by the
DSP after the rising edge of CCLK for the D2 bit,
REQ will be immediately re-asserted, thus creating
a pulse on REQ. The byte in the SCP out register
may be read by the bus master as part of the current
transaction or may be read later as part of a new
read transaction.
The CS4812 has a MAP auto increment capability
which allows block reads or writes of successive
control port registers.This feature is enabled by set-
ting the INCR bit in the MAP byte.
During a write sequence, multiple bytes may be
written by continuing to send data bytes to the
CS4812 after the first data byte and before de-as-
serting CS. If auto increment is disabled, the last
data byte sent will appear in the register designated
by the MAP. If auto increment is enabled, data
bytes sent following the first data byte will be writ-
ten to successive registers following that designat-
ed in the MAP.
22
DS291PP3
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